Input_pre_tb.v

1. 读取txt文件的输入 28*28
2. bram烧录权重coe
3. 编写tb的控制逻辑

layer1_output_test.m

w_a=bitor( bitshift(buffer(1), 0),bitshift(buffer(2),8)); w_b=bitor( bitshift(buffer(3),16),bitshift(buffer(4),24)); w_four_in_one=bitor(w_a,w_b); fprintf(ch3_w3,'%d,\n',w_four_in_one);

cnt=1;
ch0_w0=fopen('ch0_w0.coe','w');
fprintf(ch0_w0,'memory_initialization_radix=10;\\n');
fprintf(ch0_w0,'memory_initialization_vector=\\n');
for n=1:4:32
    for k=1:4:32
        for i=1:3
            for j=1:3  
                   if(w_2(i,j,k,n)<0)
                        w_2(i,j,k,n) =  w_2(i,j,k,n)+2^8;
                   else
                        w_2(i,j,k,n)=   w_2(i,j,k,n);
                   end
                   buffer(cnt)= w_2(i,j,k,n);
                   if(cnt==4)      
                        w_a=bitor( bitshift(buffer(1), 0),bitshift(buffer(2),8));
                        w_b=bitor( bitshift(buffer(3),16),bitshift(buffer(4),24));
                        w_four_in_one=bitor(w_a,w_b);
                        fprintf(ch0_w0,'%d,\\n',w_four_in_one);  
                        cnt=1;
                   else
                        cnt = cnt+1;
                   end
                   
            end
        end
    end
end

dma_write_last0 这个信号什么时候回置为1呢？

dma_write_last0决定了我卷积是否能开始 每次清零后才能重置吗？

测试结果代码

//the code below is for convlutional module in simulation  --shichaofan
reg [4:0]cnt_pool;

integer pool;

initial
begin
 pool  =  $fopen("C:/Users/Allen/Desktop/minst_vfinal/matlab_minst1/pool_out0_channel0.txt");
end
always@(posedge clk)
begin
    if(!rst_n)
    begin
       cnt_pool=0;
    end
    else
    begin
      if(valid_out_pool)
        begin
          $fdisplay(pool,"%d",data_out_pool);
        end
     end
end

always@(posedge pool_end)
begin 
    if(cnt_pool==3) begin
        $fclose(pool);   
    end
    else begin
        cnt_pool=cnt_pool+1;
    end
end

//the code below is for convlutional module in simulation  --shichaofan
reg [4:0]cnt_conv;

integer conv;

initial
begin
 conv  =  $fopen("C:/Users/Allen/Desktop/minst_vfinal/matlab_minst1/add4_out0_channel0.txt");
end
always@(posedge clk)
begin
    if(!rst_n)
    begin
       cnt_conv=0;
    end
    else
    begin
      if(dataout_valid_add4)
        begin
          $fdisplay(conv,"%d",data_out_add4);
        end
     end
end

always@(posedge conv_end_add4)
begin 
    if(cnt_conv==3) begin
        $fclose(conv);   
    end
    else begin
        cnt_conv=cnt_conv+1;
    end
end

//the code below is for convlutional module in simulation  --shichaofan
reg [4:0]cnt_relu;

integer relu;

initial
begin
 relu  =  $fopen("C:/Users/Allen/Desktop/minst_vfinal/matlab_minst1/relu_out0_channel0.txt");
end
always@(posedge clk)
begin
    if(!rst_n)
    begin
       cnt_relu=0;
    end
    else
    begin
      if(acc_bias_data_out_valid)
        begin
          $fdisplay(relu,"%d",acc_bias_data_out);
        end
     end
end

always@(posedge acc_end)
begin 
    if(cnt_relu==3) begin
        $fclose(relu);   
    end
    else begin
        cnt_relu=cnt_relu+1;
    end
end

minst_vfinal.7z